The present application pertains to timekeeping circuits and, more particularly, to low power timekeeping circuits.
Most computers include a timekeeping module or system which keeps track of the present time of day and date using its own oscillator. These timekeeping systems receive their primary power from the computer system but have backup batteries in order to preserve the time data when the primary power source fails. Since the useful life of the backup battery depends generally on the amount of current drawn by the timekeeping system, the power supply current used by the timekeeping system generally determines how often battery replacement is required. Therefore it can be appreciated that a timekeeping system which operates with a relatively small amount of power supply current is highly desirable.
The disclosed innovations provide a timekeeping system which requires only a relatively small amount of power supply current.
In the preferred embodiment, the timekeeping chip keeps time by a process of:
(1) reading seconds data from a memory, incrementing the seconds data, and storing the incremented seconds data back into the memory.
(2) If the seconds data, before being incremented, was 59 seconds, then the minutes data is read, incremented, and the incremented minutes data is stored in the memory.
(3) If the minutes data, prior to being incremented, was at 59 minutes, then the hours data is read from the memory, incremented, and the incremented hours data is stored back into the memory.
In the present invention, this method is combined with an innovative circuit architecture. Separate busses are used for the time data and for the alarm data. This allocation of functions to separate busses has been found to have substantial advantages of power consumption.
This provides a software-based timing operation wherein the power-consumption is extremely low. On the time bus, the higher-order (minutes etc.) data is not fetched unless the time seconds data is 59, or matches the alarm seconds data. Therefore, during 58 of every 60 seconds, the data is merely incremented, so that the higher-order bits may or may not change. Similarly, the data on the alarm bus remains constant for 59 seconds out of every 60. Thus, charge consumption due to charge and discharge cycles is minimized.
It should be noted that the disclosed data bus architecture also cooperates advantageously with the disclosed ratioless programmable array logic. This array logic, in the presently preferred embodiment, provides "break-before-make" operation, which avoids through currents.
The preferred embodiment provides a timekeeping system which includes a sequencer, a memory, and an accumulator connected together by a data bus. The stored seconds data is outputted onto the data bus from the memory, and read by the accumulator. The accumulator increments the seconds data and writes the incremented seconds data onto the data bus. The incremented seconds data is stored in the memory, and the memory holds the incremented seconds data on the data bus until at least a next read operation by the memory or a next write operation by the accumulator.